1. Field of the Invention
The present invention relates to a semiconductor memory device (e.g., an IC memory card) utilizing a boot block flash memory; a boot block flash memory control circuit used for such a semiconductor memory device; and an erasure method for a boot block flash memory.
2. Description of the Related Art
Flash memories can be classified into symmetrical block flash memories and boot block flash memories. A symmetrical block memory includes xe2x80x9csymmetrical blocksxe2x80x9d, i.e., blocks having the same capacity. A boot block flash memory includes both symmetrical blocks and boot blocks, such that each boot block has a different capacity from that of each symmetrical block. Conventionally, a majority of flash memory-based IC memory cards, as shown in FIG. 12A, adopt a symmetrical block flash memory structure having symmetrical blocks of e.g., 64 kbytes. Therefore, conventional IC memory card applications often incorporate card controlling software intended for such IC memory cards of a symmetrical block flash memory type. Such card controlling software is not intended for IC memory cards of a boot block flash memory type.
Accordingly, there is a problem in that a majority of IC memory card applications on the market, whose card controlling software cannot be updated, can only utilize IC memory cards of a symmetrical block flash memory type.
Furthermore, an IC memory card of a boot block flash memory type as shown in FIG. 12B, may have a different boot block size (capacity) from manufacturer to manufacturer. Therefore, each IC memory card product requires a specially-designed data rewriting program. This requirement detracts from their versatility.
Hence, in order for IC memory cards to be versatile, they need to utilize symmetrical block flash memories. Thus, IC memory cards of a symmetrical block flash memory type may be versatilely used with respect to IC memory card applications which are adapted thereto; however, there still remains a problem with IC memory cards of a boot block flash memory type, in that such IC memory cards cannot be versatilely used.
Accordingly, a semiconductor memory device is proposed in Japanese Laid-Open Publication No. 6-119230, for example, in which a boot block mode and a symmetrical block mode are switchable so that either a symmetrical block flash memory portion or a boot block flash memory portion thereof can be used at a time, as shown in FIGS. 13A and 13B.
However, the technique disclosed in Japanese Laid-Open Publication No. 6-119230 requires both a boot block memory and a symmetrical block memory to be provided on a chip, resulting in the problem of increased chip area and hence increased cost.
On the other hand, Japanese Laid-Open Publication No. 10-241377 discloses a semiconductor memory device featuring a boot block flash memory in which the same address counter is used for designating cells in both symmetrical blocks and irregular blocks (i.e., boot blocks), thereby attempting to reduce the scale of the circuitry.
However, when performing a block erasure, the technique disclosed in Japanese Laid-Open Publication No. 10-241377 cannot change the size of the block to be erased; i.e., the boot blocks cannot be operated in the same fashion as symmetrical blocks. As a result, this boot block flash memory is not interchangeable with a symmetrical block flash memory. Another problem associated with conventional IC memory cards is that, when erasing data in a plurality of boot blocks in an IC memory card of a boot flash memory type, a host system must designate individual ones of the plurality of boot blocks, and it is necessary to issue plural instances of an erase command.
According to one aspect of the present invention, there is provided a boot block flash memory control circuit for controlling a boot block flash memory, the boot block flash memory including at least one symmetrical block each having a first capacity and a plurality of asymmetrical blocks each having a capacity smaller than the first capacity, wherein: the boot block flash memory control circuit detects a first address signal designating an address in the boot block flash memory and a first command signal for causing the boot block flash memory to operate, and based on the detected first address signal and first command signal, outputs a second command signal and a second address signal for erasing data stored in one of the at least the one symmetrical block or a subset of the plurality of asymmetrical blocks.
In one embodiment of the invention, a total capacity of the subset of asymmetrical blocks is equal to the first capacity of the at least one symmetrical block.
In another embodiment of the invention, while data stored in the subset of asymmetrical blocks is erased, a READY signal and an operation status signal, which are similar to a READY signal and an operation status signal to be output when data stored in one of the at least one symmetrical block is erased, are output.
In still another embodiment of the invention, the boot block flash memory control circuit further includes : a boot block address detection circuit for detecting a first block designating address signal which designates the subset of asymmetrical blocks and outputting a first signal based on the first block designating address signal; a command detection circuit for outputting a second signal based on the first signal, a first block erase command signal for erasing data stored in the subset of asymmetrical blocks, and a first control signal; and an address/command generation circuit for outputting the second address signal and the second command signal to the subset of asymmetrical blocks based on the second signal and a second control signal from the boot block flash memory.
In still another embodiment of the invention, the boot block flash memory control circuit further includes a READY signal/status signal control circuit for outputting a signal indicating an erasure state while the subset of asymmetrical blocks are erased.
In still another embodiment of the invention, at least one of the plurality of asymmetrical blocks includes a boot block or a parameter block.
According to another aspect of the present invention, there is provided an IC memory card including: a boot block flash memory; and an interface IC for controlling the boot block flash memory based on an external signal, wherein the interface IC includes the aforementioned boot block flash memory control circuit.
In one embodiment of the invention, in a memory space of the boot block flash memory, a plurality of asymmetrical blocks in the boot block flash memory are decoded to an address region which is substantially unlikely to be accessed.
In another embodiment of the invention, in a memory space of the boot block flash memory, a plurality of asymmetrical blocks in the boot block flash memory are decoded so as to be deleted from the memory space.
According to yet another aspect of the present invention, there is provided a semiconductor memory device including: a host system; a boot block flash memory; and a boot block flash memory control circuit for controlling the flash memory based on a signal from the host system, wherein the boot block flash memory control circuit is the aforementioned boot block flash memory control circuit.
According to yet another aspect of the present invention, there is provided a method for erasing data stored in a boot block flash memory including a plurality of asymmetrical blocks, including the steps of: outputting a first signal based on a first block designating address signal which indicates a block designating address of a subset of the plurality of asymmetrical blocks input from the host system; outputting a second signal based on the first signal, a first block erase command signal, and a first control signal; outputting a second block designating address signal and a second block erase command signal to the boot block flash memory, based on the second signal and a second control signal from the boot block flash memory; and outputting to the host system a signal indicating an erasure state of the boot block flash memory while erasing data stored in a subset of a plurality of asymmetrical blocks in the boot block flash memory.
In one embodiment of the invention, the plurality of asymmetrical blocks are decoded in such a manner that erasure of data stored in the plurality of asymmetrical blocks is prohibited irrespective of the first block designating address signal which is input from the host system.
Hereinafter, the effects of the present invention will be described.
According to the present invention, in order to make it possible to utilize a boot block flash memory in the same manner as a symmetrical block flash memory, a boot block flash memory control circuit is provided in an interface portion of a boot block flash memory. When a first erase command signal and a first address signal are issued from a host system, the boot block flash memory control circuit can detect that the address signal designates a subset of a plurality of asymmetrical blocks. Then, the boot block flash memory control circuit outputs a second address signal and a second erase command signal for performing a data erasure for the subset of asymmetrical blocks. As a result, as described in Example 1 below, the data stored in the subset of asymmetrical blocks can be erased by only a single instance of a first erase command signal issued from a host system. The host system is not required to issue a plurality of instances of the first block erase command signal while switching the first block designating address signal, unlike in conventional systems. Moreover, the host system can deal with a subset of a plurality of asymmetrical blocks as if one virtual block.
According to the present invention, it is preferable to perform a data erasure for a number of asymmetrical blocks so that the combined capacity of such asymmetrical blocks becomes equal to the capacity of each symmetrical block present in the boot block flash memory. As a result, as described in Example 2 below, the size of the blocks to be erased can be unified, so that operations on an IC memory card including boot blocks can properly take place by employing a host system containing software which is designed for IC memory cards of a symmetrical block flash memory type. In this case, the asymmetrical blocks within such a group of combined asymmetrical blocks can be erased in a sequential manner.
Furthermore, according to the present invention, all of asymmetrical blocks in a boot block flash memory may be decoded to address regions within a memory space which are least likely to be accessed by a host system. In this case, as described in Example 3 below, all asymmetrical blocks can be concentrated in regions within the memory space of the IC memory card which are least likely to be accessed by a host system, but the host system can still access the boot blocks. When a user uses an IC memory card, there is a general tendency that the memory space is accessed beginning from the first address. Therefore, by ensuring that the asymmetrical blocks are decoded to the vicinity of the last address in the memory space, the probability of the asymmetrical blocks being made any use of is advantageously minimized.
On the other hand, the block erase time required for a symmetrical block is four times as long as the block erase time required for a virtual symmetrical block (in which asymmetrical blocks are sequentially erased). By placing the asymmetrical blocks in the vicinity of the last address, which is less likely to be accessed, any deterioration in performance which would otherwise occur can be prevented.
Alternatively, according to the present invention, an asymmetrical block section may be decoded so as to be deleted from the memory space (hereinafter such decoding will be referred to as a xe2x80x9cdeletion-decodexe2x80x9d), so that a host system cannot access the asymmetrical blocks in a boot block flash memory corresponding to addresses which are input from the host system. In this case, as described in Example 4 below, the asymmetrical blocks are deleted from the memory space of the IC memory card, so that the host system is prevented from accessing the boot block section.
As described above, the block erase time required for a symmetrical block is four times as long as the block erase time required for a virtual symmetrical block (in which asymmetrical blocks are sequentially erased). Therefore, card controlling software which is designed for IC memory cards of a symmetrical block flash memory type may run the risk of overflowing a wait time which is associated with an erase time for a particular IC memory card. Accordingly, an IC memory card can be constructed which has a memory space only including symmetrical blocks and no asymmetrical block sections, whereby operations can occur satisfactorily.
Furthermore, according to the present invention, while a subset of a plurality of asymmetrical blocks are being subjected to a data erasure, a READY signal and an operation status signal similar to those used while a host system is performing a data erasure for a symmetrical block may be output to the host system. As a result, as described in Example 5 below, the data erasure for the subset of asymmetrical blocks appears to the host system as if an erase operation for a single symmetrical block.
Thus, the invention described herein makes possible the advantages of: (1) providing a boot block flash memory control circuit which, with an erase command signal for erasing data in one symmetrical block of a boot block flash memory, is capable of erasing data in a plurality of asymmetrical blocks, and which can avoid increase in the chip area of a single flash memory structure; an IC memory card and a semiconductor memory device incorporating such a boot block flash memory control circuit; and an erasure method for the boot block flash memory, and (2) providing a boot block flash memory control circuit which allows a plurality of asymmetrical blocks to be operated as symmetrical blocks, and which allows IC memory cards to be versatilely used with conventional IC memory card applications in the same fashion as a symmetrical block flash memory; an IC memory card and a semiconductor memory device incorporating such a boot block flash memory control circuit; and an erasure method for the boot block flash memory.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.